Computer+Structure+Busses

Busses__
 * __Computer Structure

Information has to be transferred backwards and forwards between memory and the processor. Busses are used to do this. A bus is a group of cables where each cables can transmit a bit.

There are three different types of busses: **
 * **Address Bus** - Used by the processor to locate the memory location needed. This bus only transmits data one way (uni-directional)
 * **Data Bus** - Used to transfer the data from the processor to memory, and from memory to the processor. This is able to transmit data both ways(bi-directional)
 * **Control Bus** - Is used to tell memory, what is happening. The control bus is not a true bus because each line is used independently and does nnot send or recieve data

__**Control Bus**__ The control bus usually consists of the following control lines:


 * **Read** - A signal from the processor that initiatives a memory read operation (sends data from memory to the processor) once thet address bus and the data bus have been set up.


 * **Write** - A signal from the processor that initiates a memory write operation(sends data from the processor to memory) once the address bus and data bus have been set up.


 * **Clock** - Every processor has a clock which ticks continuously and is used by the control unit to tell all the components when certain tasks have to be done. Current processors have clock speeds of 2.4GHz which 'ticks' 2,400,000,000 times per second. Larger clock speed = faster.


 * **Reset** - This clears all internal processor registers and starts fetching instructions from a predefined place.


 * **Interrupt** - This causes the current state of processing to be saved in a temporary area (called the stack). The processor then deals with the device that made the interrupt, returning to the previous operation when the interrupt is complete. INstructions can tell the processor to ignore of 'mask' the interrupt system.


 * **Non Maskable INterrupt (NMI)** - This operates in the same way as the 'interrupt' signal except that it cannot be masked(ignored). The processor must deal with this interrupt.